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mas 3528e dolby digital and mpeg-1 layer-2 edition june 28, 2000 6251-509-1ai advance information micr onas micronas audio decoder
mas 3528e advance information 2 micronas contents page section title 5 1. introduction 5 1.1. features 6 1.2. system application 7 1.3. application details 8 2. functional description 82.1.overview 8 2.2. architecture 8 2.3. dsp core 9 2.4. internal program rom and firmware 9 2.5. ram and registers 9 2.5.1. program download feature 9 2.6. clock management 10 2.7. interfaces 10 2.7.1. i 2 c control interface 10 2.7.2. s/pdif-input interface 10 2.7.3. s/pdif-output 10 2.7.4. serial input interface 10 2.7.4.1. multiline serial output 10 2.7.5. frame synchronization 11 2.8. power-supply regions 11 2.9. functional blocks and operation 11 2.9.1. power-up sequence and default operation 12 2.9.2. input switching 12 2.9.3. standard selection and decoding 12 2.9.4. dolby digital data stream 12 2.9.5. mpeg layer-2 data stream 12 2.9.6. pcm audio data 12 2.9.7. deemphasis 12 2.9.8. channel expander 13 2.9.9. noise generator 13 2.9.10. post processing / bass management 13 2.9.10.1. downmix 13 2.9.10.2. digital volume 13 2.9.10.3. bass management 14 2.9.11. output format selection 15 2.9.12. dts / s/pdif loop-through 15 2.9.13. output sampling rate 15 2.10. system interaction 15 2.10.1. minimum required interconnections 15 2.10.2. required special modes in the system 16 2.10.3. minimum system set-up
contents, continued page section title advance information mas 3528e micronas 3 17 3. control interface 17 3.1. start-up sequence 17 3.2. i 2 c interface access 17 3.2.1. general 17 3.2.2. i 2 c registers and subaddresses 17 3.2.3. conventions for the command description 18 3.2.4. the internal fixed point number format 18 3.3. i 2 c control register (subaddress 6a hex ) 18 3.4. i 2 c data register (subaddresses 68 hex and 69 hex ) and the mas 3528e dsp-command syntax 19 3.4.1. run and freeze 20 3.4.2. read register 20 3.4.3. write register 20 3.4.4. read d0 memory 20 3.4.5. short read d0 memory 21 3.4.6. read d1 memory 21 3.4.7. short read d1 memory 21 3.4.8. write d0 memory 21 3.4.9. short write d0 memory 21 3.4.10. write d1 memory 22 3.4.11. short write d1 memory 22 3.4.12. default read 23 3.5. registers 24 3.6. special memory locations and user interface 24 3.6.1. status interface for decoding 32 3.6.2. control interface for decoding operation 40 3.6.3. hybrid user interface cells 41 4. specifications 41 4.1. outline dimensions 41 4.2. pin connections and short descriptions 43 4.3. pin descriptions 43 4.3.1. power supply pins 43 4.3.2. control lines 43 4.3.3. parallel interface lines 43 4.3.4. clocking 43 4.3.5. serial input interface 44 4.3.6. s/pdif input interface 44 4.3.7. s/pdif output interface 44 4.3.8. serial output interface 44 4.3.9. miscellaneous 44 4.4. pin configuration 45 4.5. internal pin circuits 46 4.6. electrical characteristics 46 4.6.1. absolute maximum ratings 47 4.6.2. recommended operating conditions 47 4.6.2.1. general recommended operating conditions
mas 3528e advance information 4 micronas contents, continued page section title 47 4.6.2.2. reference frequency generation and crystal recommendations 47 4.6.2.3. input levels at v dd = 4.5 v...5.5 v 48 4.6.3. characteristics 48 4.6.3.1. general characteristics 49 4.6.3.2. i 2 c characteristics 50 4.6.3.3. s/pdif-bus input characteristics 51 4.6.3.4. s/pdif-bus output characteristics 52 4.6.3.5. i 2 s bus characteristics ? input 54 4.6.3.6. i 2 s characteristics ? output 55 4.6.4. firmware characteristics 60 5. data sheet history references 1. digital audio compression (ac-3), atsc standard, advances television systems committee, james c. mckinney, chariman, dr. robert hopkins, executive director (dec. 20, 1995) 2. dolby licensee information manual: dolby digital consumer decoder, issue 3, 1999 license notice dolby-b-nr, dolby digital, dolby pro logic, and dolby surround sound are trademarks of dolby laboratories. supply of this implementation of dolby technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of dolby laboratories, to use this implementation in any finished end-user or ready-to-use final product. companies planning to use this implementation in products must obtain a license from dolby laboratories licensing corporation before designing such products.
advance information mas 3528e micronas 5 dolby digital and mpeg-1 layer-2 audio decoder 1. introduction the micronas mas 3528e is a single-chip dolby digi- tal and mpeg-1 layer-2 decoder. together with the surround sound processor dpl 4519g, it acts as a complete implementation of a dolby digital consumer decoder. in a television environment, these two inte- grated circuits are complemented by the micronas mul- tistandard sound processor msp 4450g which per- forms the standard tv sound decoding. 1.1. features ? s/pdif, iec-958, iec 61937, aes/ebu, eia-j cp- 340 receiver (2 multiplexed inputs) ? two freely configurable multiplexed serial inputs ? decoders for 5.1-channel dolby digital (ac-3) and mpeg-1 layer-2 ? handling of pcm input format ? s/pdif loop-through for dts (digital theater sys- tem) and pcm formats ? optional surround encoding (lt, rt) or straight downmixing to two channels (lo, ro) ? multi-channel i 2 s output (four stereo data lines or one 8-channel line) ? dynamic range compression ? karaoke downmixing ? delay for center (0 5ms) ? delay for surround (two channels, 0 15 ms) ? bandpass-shaped/white-noise generator ? bass management according to dolby specification (output configuration 0, 1, 2, 3, and dvd) ? i 2 c-control fig. 1?1: block diagram mas 3528e table 1?1: ics used for the dolby digital system solution type description msp 4450g multistandard sound processor with 48 khz processing dpl 4519g sound processor for digital and analog surround systems mas 3528e dolby digital/mpeg-1 decoder s/pdif in serial in i 2 s i 2 s clock pio serial out i 2 s s/pdif out risc dsp core s/pdif in serial inputs serial control s/pdif out i2s output additional inputs and outputs /9+3/ (dolby digital, mpeg-1 layer-2, pcm) clko xto xti 18.432 mhz mas 3528e
mas 3528e advance information 6 micronas 1.2. system application the micronas dolby digital system solution consists of three dedicated integrated circuits: ? the msp 4450g is the interface for all tv-sound and analog input signals. it performs the tv-audio demodulation including analog stereo, nicam, and wegener panda decompression. it has four pairs of audio d/a-converters, two of them including sound control facilities, and one additional subwoofer d/a- converter. ? the dpl 4519g adds the dolby surround sound features and has three pairs of audio d/a-convert- ers, two of them including sound control facilities, and one additional subwoofer d/a converter. ? the mas 3528e performs the dolby digital or mpeg decoding and has additional functions that are necessary for the dolby digital system. while the msp 4450g is a stand-alone tv-sound solu- tion, the combination with a dpl 4519g results in a high-end tv with dolby pro logic functionality. with the addition of the mas 3528e, the tv provides full dolby digital/mpeg-1 capabilities. a combination of the dpl 4519g with the mas 3528e is a fully functional dolby digital integration for multi- media applications with a total of seven high-quality audio d/a-converters. fig. 1 ? 2: configuration of the micronas dolby digital tv system solution. tv s/pdif out mas 3528e s/pdif i 2 s/serial dvd dvb dpl 4519g msp 4450g tu n e r vcr l/(sub)/r or l/(c)/r i 2 s sl/sr l/(sub)/r or l/c/r or c/c lt/rt or lo/ro scart scart (tv+stereo) i 2 s i 2 s scart 1...6 ch 1...8 ch 8 ch 8 ch 2 ch 1...8 ch if pcm/dolby digital mpeg via i2s serial
advance information mas 3528e micronas 7 1.3. application details fig. 1 ? 3: block diagram of a mas 3528e in a television environment with all d/a-converters shown. dpl 4519g prologic decoder i2s_ws3 i2s_cl3 6 channel loop-through or dolby pro logic decoder i2s_1_l i2s_1_r i2s_3_r t i2s_3_l t audio_ cl_out sif-in i2s_ws i2s_cl speaker headphone i2s_ws i2s_cl demod scart1_in scart4_in a/d 2 . . . i2s_2_l i2s_2_r r l s l sub bass treble balance volume bass treble balance volume msp 4450g multistandard sound processor i2s_1_l i2s_1_r i2s_2_l i2s_2_r sound- process. balance volume bass treble balance volume volume volume 18.432 mhz i 2 s_inputs 123 123 i 2 s_inputs d/a analog volume d/a d/a i2s_ws3 i2s_cl3 configuration examples 2-8 channel serial input i2s_3_l t i2s_3_s l speaker headphone scart1 scart2 normal d/a analog volume d/a analog volume d/a analog volume c int c int l t r t l t r t l, r l ext sub ext dolby digital / pro logic s l s r c int sub ext l, r c, sub sl, sr l t , r t l int r int subw int l t r t l t r t l, r --- --- --- --- --- l r subw l r l r l, r subw int 12 basic tv- sound system dolby digital upgrade module l, r c, sub sl, sr l t , r t 18.432 mhz dolby digital: (l t , r t , l, r, s l , s r , c, sub) prologic: (l t , r t , l, r, c, subw) i2s_out_l/r i2s_out_l/r s l s r i2s_3_r i2s_3_sub s/pdif out pcm-format (lt/rt or l/r or lo/ro) or loop through (e.g. dts) 18.432 mhz i 2 s-mode:multichannel mode on d0 (6 - 8 channels, fs=32, 44.1 or 48 khz, 16,18,....32 bit) i 2 s-in: slave l t r t --- --- l t r t 2 volume d/a scart1 i2s_3_r t r ext (c int ) --- l t r t l t r t l r i2s_3_l i2s_3_s r i2s_3_c 2-8 ch. input (l t , r t ,l, r s l , s r ,c, sub) s r c dolby digital / pro logic configurations example 1: - internal l,c,r - internal woofer for low freq. of l,(c),r - ext.surround speakers s l ,s r - ext.subwoofer for sub channel. example 2: - internal left and right used as c - internal woofer for low freq. of c - ext. l,r - ext. surround speakers s l ,s r - ext. subwoofer for sub channel. mas 3528e dolby digital decoder mpeg l2 decoder sic sii sid sic* sii* sid* soc soi sod sod1 sod2 sod3 input buffer deemphasis post processing delay lines ac-3 pcm mpeg l r lt rt ls rs amp./ osc. pll synth. clko noise gen. multipl. c/ sub spdo s/pdif in 1/2 ac3, mpeg l2 or pcm format
mas 3528e advance information 8 micronas 2. functional description 2.1. overview the mas 3528e is intended for use in high-end con- sumer audio applications. it receives s/pdif or serial data streams and decodes the dolby digital (ac-3), mpeg or pcm-encoded audio formats. due to the automatic format detection, no controller interaction is needed for the standard operation. on the other hand, the controller has full access to all vital information contained in the dolby digital bit stream. the choice of different output formats, as defined by dolby, guarantees good adaption to various listening environments. 2.2. architecture the hardware of the mas 3528e consists of a high performance risc digital signal processor (dsp) and appropriate interfaces. fig. 2 ? 1 shows a hardware overview of the ic; fig. 2 ? 2 on page 11 shows the functional aspects. 2.3. dsp core the internal processor is a dedicated audio dsp. all data input and output actions are based on a ? non cycle stealing ? background dma that does not cause any computational overhead. fig. 2 ? 1: the mas 3528e architecture alu mac accumulators registers d0 ? ram d1 ? ram rom s/pdif input interface serial input interface i 2 c slave interface quartz osc./ clock input system clock synthesizer divider divider reference clock processor clock sod3 sod2 sod1 sod s/pdif output interface pio interface parallel port s/pdif i 2 s serial audio additional i 2 s data lines clko xto xti 18.432 mhz i 2 c-bus to controller serial audio (i 2 s) s/pdif mas 3528e dsp-core
advance information mas 3528e micronas 9 2.4. internal program rom and firmware the firmware implemented in the program rom of the mas 3528e provides dolby digital decoding including the required downmixing, output configurations and delay lines (part of an implementation of dolby digital), mpeg-1 layer-2 audio data decompression, handling of pcm-encoded audio, and loop-through of dts-for- mats received via the s/pdif-input. for pcm and mpeg-signals, a deemphasis can be applied to achieve a flat frequency response as required by dolby pro logic decoders. on power-on, the dsp starts the firmware in an auto- matic standard detection mode with the s/pdif-input selected. therefore, only minimal controlling is neces- sary. in addition, the i 2 c-interface provides a set of i 2 c instructions that give access to internal dsp-registers and memory areas. 2.5. ram and registers the dsp-core has access to two ram-banks denoted d0 and d1. all ram-addresses can be accessed in a 20-bit or a 16-bit mode via i 2 c-bus. for more details, please refer to section 3.4. on page 18. for fast access of internal dsp-states, the processor core has an address space of 256 data registers (see section 3.5. on page 23) which can be accessed via i 2 c-bus. 2.5.1. program download feature the overall function of the mas 3528e can be altered by downloading up to 4 kwords of program code into the internal ram and executing this code instead of the rom code. while using such alternate program code, no dolby digital or mpeg-decoding is possible. all information concerning the download feature will be distributed together with the download code. 2.6. clock management the mas 3528e is driven by a single clock at a fre- quency of 18.432 mhz. the clock may either be pro- vided from an external source to pin xti or generated with a crystal. at pin xto, the clock signal is available for other applications. the internal reference clock and processor clock are derived from the 18.432 mhz and synchronized to the audio sample frequency of the decompressed bit stream by a pll. in case of dolby digital decoding, the clock frequency may be selected between a high and a low value by bit[16] in configuration memory cell uic_out_clk_scale (d0:13df) ? (see table 3 ? 7 on page 32). the resulting processor clocks are given in table 2 ? 1. at pin clko, a clock output can be provided e.g. for additional d/a-converters. the output frequency at clko is the reference clock divided by a factor as selected by bits[18:17] in d0:13df. by default, clko is disabled.. table 2 ? 1: processor clock frequencies in dependence of bit[16] of uic_out_clk_scale (d0:13df). format f s /khz processor clock/mhz bit[16] = 0 bit[16] = 1 dolby digital 48 61.44 73.728 44.1 56.448 67.7376 32 40.96 49.152 mpeg, pcm 48 36.864 44.1 33.8688 32 24.576 table 2 ? 2: reference clock frequencies in dependence of bit[16] of uic_out_clk_scale (d0:13df). format f s /khz reference clock/mhz bit[16] = 0 bit[16] = 1 dolby digital 48 61.44 73.728 44.1 56.448 67.7376 32 40.96 49.152 mpeg, pcm 48 73.728 44.1 67.7376 32 49.152
mas 3528e advance information 10 micronas 2.7. interfaces the mas 3528e uses an i 2 c-interface for control pur- poses. two kinds of digital audio inputs are provided: s/pdif and a configurable serial input interface. both inter- faces can be used for digital audio data input in the pcm, ac-3 (dolby digital), or mpeg format. for the audio output, a serial multiline interface can be used in different i 2 s-like modes providing up to 8 audio channels. the s/pdif-output can carry the pcm-audio information or can be used in a loop-through function. 2.7.1. i 2 c control interface for controlling and program download purposes, a standard i 2 c-interface is implemented. a detailed description of all functions can be found in section 3. on page 17 2.7.2. s/pdif-input interface the s/pdif interface is a one wire serial bus signal. in addition to the signal input pins spdi/spdi2, a refer- ence pin spref is provided to support balanced sig- nal sources or twisted pair transmission lines. the fol- lowing features are supported: ? fast synchronization on input signal (<50 ms) ? burst-mode support for dolby digital (ac-3) and mpeg-bitstreams ? locking on 32, 44.1, 48 khz sample frequencies ? incoming first 20 channel status bits are mirrored in reg. 56 hex (see table 3 ? 5 on page 23) 2.7.3. s/pdif-output at pin spdifout, the baseband audio is provided as an s/pdif-signal. channel status bits in s/pdif output (especially copy- right, category code, and generation status) can be configured in d0:13ea (see table 3 ? 7 on page 32). alternatively, this output can mirror the unprocessed signal of the s/pdif-input (output_conf: register 2e). this loop-through is necessary for dts (digital the- ater system) signals where no internal decoding action is performed. 2.7.4. serial input interface if the serial input interface carries dolby digital, mpeg layer-2, or pcm, the mas 3528e processes the data. the interface consists of the three pins: sic, sii, and sid. for mpeg and dolby digital decoding operation, the sii pin must always be connected to v ss , while for pcm-data, the interface acts as an i 2 s-type and sii is used as a word strobe. an example of an input signal format is shown in fig. 4 ? 17 on page 53. the data val- ues are latched with the falling edge of the sic signal. it is possible to use a word length of 16 or 32 bits. for controlling details, please refer to memory address d0:13d0 (i/o control) and d0:13df (auxiliary inter- face control) in table 3 ? 7 on page 32. if the mpeg or dolby digital signal was formatted (e.g. to 8-bit or 16-bit words) by the storing or transportation medium (pc, memory), the serial data must be sent ? msb first ? as produced by the encoder. 2.7.4.1. multiline serial output the serial audio output interface of the mas 3528e is a standard i 2 s-like interface consisting of four data lines sodx, the word strobe soi, and the clock signal soc. the output bitstream can either carry eight chan- nels on one line (sod) or two channels on each of four lines (sod, sod1, sod2, sod3). furthermore, it is possible to choose between different interface configu- rations (with word strobe time offset and/or with inverted soi-signal). the serial output generates 32 bits per audio sample, but only the first 20 bits will carry valid audio data. the 12 trailing bits are set to zero by default (see fig. 4 ? 19 on page 54). the configuration of the output interface is done in d0:13d0 and d0:13df (see table 3 ? 7 on page 32). 2.7.5. frame synchronization for microprocessor interrupts, a frame synchronization output pin (sync) is provided. after decoding a valid header, the sync pin level changes to high. most of the status information (uis cells in table 3 ? 6 on page 24) is updated now. to gen- erate an edge for the controller, the level changes to low during processing the next header. after having completed this, the sync pin level changes to high again. if the level is low for more than 1 ms, no decod- ing is performed. memory cell uih_last_error (d0:13ff) provides background information thereof.
advance information mas 3528e micronas 11 notes for dolby digital: after first crc is done, the sync pin level changes to high, all information for a frame is valid, and decoding is performed. the sync pin level changes to low before new status information is written. please take into account that uis_dynrng, uis_dynrng2, and uis_karaokeflag are valid for the audio block only; the sync pin does not signalize their validity. notes for mpeg: after processing crc, the sync pin level changes to high, all information for a frame is valid, and decoding is performed. the sync pin level changes to low before evaluating new header information. 2.8. power-supply regions the mas 3528e has three power supply regions. the vdd/vss-pin pair supplies all digital parts including the dsp-core.the xvdd/xvss-pin pair is connected to the signal pin output buffers.the avdd/avss-sup- ply is for the clock oscillator, pll-circuits, and system clock synthesizer. 2.9. functional blocks and operation a block diagram of the mas 3528e functionality is shown in fig. 2 ? 2. 2.9.1. power-up sequence and default operation after applying the appropriate voltages to the three supply pins and releasing the reset signal, the circuit starts normal operation with the s/pdif as the expected input and automatic standard recognition (dolby digital, mpeg, pcm). no further action is nec- essary for default operation or dts loop-through. a power-on reset can be issued at any time via pin por . when the input format is changed (e.g. from dolby digital to mpeg), the synchronization is lost and the audio output is muted. the automatic standard recog- nition then checks the new input format and, after suc- cessful recognition, resumes normal operation. fig. 2 ? 2: functionality of the mas 3528e 1 2 3 4 5 6 7 8 2 9 input buffer pcm mpeg layer-2 ac-3 decoder deemphasis 2 6 channel expander post processing delay lines lt/rt/ lo/ro l/r ls/rs c/sub multiplexer div div synthesizer pll amp./ oscill. 18.432 mhz noise generator 6 6 2 2 26 2 2 2 2 8 output buffers buffer fill information reference clock processor clock s/pdif inputs serial inputs clock / quartz sod sod1 sod2 sod3 s/pdif output clko mas 3528e
mas 3528e advance information 12 micronas 2.9.2. input switching both input interfaces, the s/pdif (default in fig. 2 ? 2) or the serial input interface, may carry any of the three data formats: dolby digital (ac-3), mpeg layer- 2, or pcm. the filling status of the input buffer repre- sents the data rate and therefore controls the system clock. the input interface can be selected in d0:13d0. the dts-format can only be received via the s/pdif- interface for loop-through. 2.9.3. standard selection and decoding in the default mode, an automatic standard recognition (auto-detection) selects the decoding algorithm according to the data format at the s/pdif-input. the detected standard is shown in the global operating status (d0:13bb). the standard selection for the i 2 s inputs can be selected manually in d0:13d0 . 2.9.4. dolby digital data stream the digital input signal can either be an s/pdif or an i 2 s-source. in the dolby digital mode, the ic performs the following tasks: ? data input with clock synchronization ? s/pdif-channel selection (one of eight possible) ? decoding of ac-3 bitstream elements ? compression control for dolby digital signals (do:13d7...13d9) ? output mode control ? dolby bass management ? center and surround delays ? dynamic compression and level adaption if the signal source is the s/pdif-input, the controller may select one of eight content channels depending on availability (d0:13bc). the respective service infor- mation is displayed in cell bit stream mode (d0:13a2). the bit stream elements contain all necessary infor- mation required to correctly handle the audio. all ele- ments important for controller actions are displayed in the status memory (see table 3 ? 6 on page 24). the mas 3528e decodes all dolby digital formats from 1 to 5.1 audio channels. accordingly, one to six of the output channels are used for the decoded audio. the output mode is selected in d0:13d6. an additional downmix pair can either be dolby surround encoded (lt, rt) or plain stereo (lo, ro; d0:13de). if the dolby digital input only contains a stereo pair, the controller must recognize this (dolby surround mode d0:13a6) and should activate an external pro logic decoder (e.g. in the dpl 4519g). 2.9.5. mpeg layer-2 data stream in the mpeg mode a valid mpeg-1 layer-2 data sig- nal is expected. the steps for decoding are ? clock synchronization to data input ? s/pdif-channel selection (one of eight possible) ? side information extraction ? audio data decompression ? optional deemphasis ? digital volume if the signal source is the s/pdif-input, the controller may select one of eight content channels depending on availability (d0:13bc). 2.9.6. pcm audio data if the pcm-data are received via i 2 s-bus, the mas 3528e expects a valid word strobe. the pcm-bitstream does not contain information about the sample rate. therefore, the controller must get this information from the signal source and set the sample rate in d0:13db accordingly. 2.9.7. deemphasis for the pcm- and mpeg-formats a deemphasis can be applied to the signal (d0:13e0). this is neces- sary because the possibly following dolby pro logic encoding requires a flat audio frequency response. for mpeg-encoded audio and via s/pdif transmitted pcm, this block is activated automatically. for proper operation of pcm signals via i 2 s, the controller has to determine whether the pcm signals have been pre- emphasized or not. 2.9.8. channel expander the outputs of the pcm/mpeg-decoders consist of two channels each; the output of the dolby digital decoder may have any number between one and six (5.1) channels. to unify the output format between dif- ferent modes the audio is always mapped to six chan- nels .
advance information mas 3528e micronas 13 2.9.9. noise generator a bandpass-shaped or white noise signal can be routed to any combination of the six main output chan- nels . the required channel sequence must be done by the controller in d0:13d1. 2.9.10. post processing / bass management the implemented post processing functions can be applied to the following audio formats. they are ? downmixing to lo/ro or surround sound encoding to lt/rt (d0:13de) for dolby digital multichannel signals ? mixing and digital filtering for the different output and bass configurations according to the dolby dig- ital licensee information manual (d0:13dd5, 13d6, 13da) ? digital volume control (d0:13e1...13e8) for all audio formats ? appropriate delay lines for center and surround channels (d0:13d2...13d4) for dolby digital multi- channel signals 2.9.10.1. downmix for headphone and vcr-recordings, a downmixed output is provided that may be switched from lt/rt (surround encoded, default) to lo/ro (headphone encoded) . the 6-channel output together with the downmix is routed to the serial data output interface . 2.9.10.2. digital volume the digital volume control provided is mainly intended for balancing purposes and initially set to 0 db. volume control, output configuration, and delays should be set by the controller according to the actual listening situa- tion. 2.9.10.3. bass management generally, not all of the five loudspeakers in a dolby digital system can reproduce the full audio bandwith. bass managment allows redirecting low frequencies to loudspeakers which are capable of reproducing this frequency range. the mas 3528e supports the following bass manage- ment modes: bass management mode 0 (d0:13da = 8) attenuation of ? 15 db in the sub channel should be compensated by a 15 db gain in the d/a-converter. fig. 2 ? 3: bass management configuration 0 bass management mode 1 (d0:13da = 9) attenuation of ? 15 db in the sub channel should be compensated by a 15 db gain in the d/a-converter. fig. 2 ? 4: bass management configuration 1 bass management mode 2 (d0:13da = a hex ) level adjustment is implemented with ? 12 db. fig. 2 ? 5: implementation of configuration 2 ? 15 db 5 ? 5db l c r ls rs lfe l c r ls rs sub + ? 15 db 5 ? 5db l c r ls rs lfe l r ls rs sub c + level adj level adj level adj + + + ? 12 db ? 12 db ? 15 db 3 ? 5db l c r ls rs lfe l c r ls rs sub ? 1.5 db ? 1.5 db
mas 3528e advance information 14 micronas bass management mode 3 (d0:13da = b hex ) fig. 2 ? 6: alternative implementation of configuration 2 bass management mode 4 (d0:13da = c hex ) fig. 2 ? 7: implementation of configuration 3 bass management mode 5 (d0:13da = d hex ) in analog part of sub should be add a +10 db gain fig. 2 ? 8: implementation of configuration three with subwoofer bass management mode 6 (d0:13da = e hex ) fig. 2 ? 9: simplified bass management for multichannel source products (i) bass management mode 7 (d0:13da = f hex ) fig. 2 ? 10: simplified bass management for multichannel source products )ii) 2.9.11.output format selection the output is an i 2 s-bus format with either eight audio channels on one line (default) or two audio channels on each of four lines ( , d0:13d0). if the 4x2-configu- ration is selected, the clock and word strobe lines soc and soi apply to all four data lines sod...sod3. clock and word strobe signals can be configured to different standards (polarity, delay). the data word length is always 32 bits. in the 1x8 format, the output data are in the following order: l, ls, c, lt/lo, r, rs, sub, rt/ro. + l c r ls rs lfe l c r ls rs sub ? 15 db 3 ? 5db l c r ls rs lfe r ls rs sub + + l c ? 4.5 db + + + l c r ls rs lfe r ls rs sub + + l c ? 4.5 db + + + l c r ls rs l c r ls rs ? 4.5 db 3 lfe sub + + + ? 5db + + l c r ls rs l c r ls rs ? 4,5 db 3 lfe ? 10.5 db ? 5db sub
advance information mas 3528e micronas 15 2.9.12.dts / s/pdif loop-through an incoming dts signal (via s/pdif) will be reflected in gos_type (d0:13bb). by default, a recognized dts signal is looped-through. this means that the signal at s/pdif input is routed to s/pdif output without processing ? regardless of bit 1 in register 2e hex . this automatism can be disabled by setting bit 12 in register 2e hex to ? 1 ? . now, the controller is to choose via bit 1 whether a pcm audio signal is output (in case of a dts signal the output is muted) or the the input data is looped-through. 2.9.13.output sampling rate the internally generated system clock is derived from the filling status of the input data buffer by a pll . this clock is synchronous to the original sampling rate and is used throughout the complete data processing. except in the ambiguous case of pcm-data at the serial audio input where the original sampling rate must be defined (d0:13db), no controller interaction is needed for clock operation. the output sampling rate is 32 khz, 44.1 khz, or 48 khz, depending on the source. since in the micronas dolby digital tv sound solution all further signal processing is on a rate of 48 khz, the input stage of the dpl 4519g performs the sample rate conversion if necessary. 2.10.system interaction 2.10.1.minimum required interconnections the mas 3528e requires the following connections for normal operation: ? power supply with adequate blocking capacitors (vdd, vss, avdd, avss, xvdd, xvss) ? crystal with capacitors or clock input (xti, xto) ? i 2 c-bus and reset-line (i2cc, i2cd) and reset line (por ) for controlling ? s/pdif-input (spdi/spdi2, spref) or serial/i 2 s- input (sid, sic, sii or sid*, sic*, sii*). in the stan- dard micronas-solution, the i 2 s-signal comes from the msp 4450g ? i 2 s-output (sod, soc, soi).in the standard config- uration, this signal is fed to the dpl 4519g. please refer to fig. 4 ? 20 on page 56 or to the applica- tion kit for details. 2.10.2.required special modes in the system the mas 3528e interfaces require no configuration. the i 2 s outputs and inputs of the dolby pro logic ic dpl 4519g and the msp 4450g, however, must be configured to send/accept the 8-channel multiplexed digital pcm-data stream. the dpl 4519g may generate up to seven analog sig- nals (three pairs plus subwoofer). further audio sig- nals can be forwarded to the msp 4450g for d/a-con- version. dolby pro logic encoded audio originating from the msp 4450g (tv-sound) must be routed through the mas 3528e to the dpl 4519g for further processing.
mas 3528e advance information 16 micronas 2.10.3.minimum system set-up the following i 2 c-command sequence is necessary for the dpl 4519g: ? i 2 c-controlled reset ? write modus register (set i 2 s-input to slave mode) ? write i2s_config (multi sample mode, 32 bits, clock to 8*32 bits) ? set i2s3 resorting matrix to ? left/right eight mas 3528e ? . the signal pairs are now in the follow- ing order: lt/rt, l/r, sl/sr, c/sub ? select first i 2 s3-input pair as source for i 2 s output (because of 8*32-bit mode all 4*2 channels will be looped through to the msp 4450g) and set to trans- parent stereo ? select one input pair as source for loudspeaker output (numbers 7...10 mean first...fourth pair) ? select one input pair as source for aux output (numbers 7...10 mean first...fourth pair) ? set volume control for loudspeaker output ? set volume control for aux output if a multistandard sound processor is present in the system, similar set-up commands are required. for further details, please refer to the dpl 4519g or the msp 4450g data sheets. if both devices are used on the same i 2 c-bus, the device addresses must be set to different values by hardware means. the d/a-conversion of audio signals may be freely appointed between the dpl 4519g and the msp 4450g. for an example, please refer to table 2 ? 4. table 2 ? 3: output configuration matrix. all registers are at i 2 c-subaddress 12 hex of the respective device. note that only one code per register applies. device dpl 4519g msp 4450g register signal pair loudsp. 00 08 hex aux 00 09 hex scart1 00 0a hex loudsp. 00 08 hex aux 00 09 hex scart1 00 0a hex scart2 00 41 hex lt/rt (lo/ro) 07 20 hex 07 20 hex 07 20 hex 07 20 hex 07 20 hex 07 20 hex 07 20 hex l/r 08 20 hex 08 20 hex 08 20 hex 08 20 hex 08 20 hex 08 20 hex 08 20 hex sl/sr 09 20 hex 09 20 hex 09 20 hex 09 20 hex 09 20 hex 09 20 hex 09 20 hex c/sub 0a 20 hex 1) 0a 20 hex 1) 0a 20 hex 1) 0a 20 hex 1) 0a 20 hex 1) 0a 20 hex 1) 0a 20 hex 1) 1) use 0a 20 hex for c/sub output, 0a 00 hex for center signal on both outputs, 0a 10 hex for sub signal on both outputs table 2 ? 4: example: in the dpl 4519g use both loudspeaker output channels for center, the auxiliary output for surround, the scart1 output for lt/rt. in the msp 4450g use the loudspeaker output for l/r, both auxiliary output channels for sub and the scart1 output for an additional lt/rt-signal. device dpl 4519g msp 4450g register signal pair loudsp. 00 08 hex aux 00 09 hex scart1 00 0aa hex loudsp. 00 08 hex aux 00 09 hex scart1 00 0a hex scart2 00 41 hex lt/rt (lo/ro) 07 20 hex 07 20 hex l/r 08 20 hex sl/sr 09 20 hex c/sub 0a 00 hex 0a 10 hex
advance information mas 3528e micronas 17 3. control interface 3.1. start-up sequence after power-up and a reset (see section 3.3. on page 18), the ic is in its default state (see table 3 ? 7 on page 32). the controller has to initialize all memory cells for which a non-default setting is necessary. 3.2. i 2 c interface access 3.2.1. general control communication with the mas 3528e is done via an i 2 c slave interface. the device addresses are 3a hex (write) and 3b hex (read) as shown in table 3 ? 1. i 2 c clock synchronization is used to slow down the interface if required. 3.2.2. i 2 c registers and subaddresses the interface uses one level of subaddresses. the mas 3528e interface has 3 subaddresses allocated for the corresponding i 2 c-registers. the address 6a hex is used for basic control, i.e. reset and task select. the other addresses are used for data transfer from/to the mas 3528e. the i 2 c-control and data registers of the mas 3528e are 16 bits wide, the msb is denoted as bit [15]. trans- missions via i 2 c-bus have to take place in 16-bit words (two byte transfers, msb sent first); thus for each regis- ter access two 8-bit data words must be sent/received via i 2 c-bus. 3.2.3. conventions for the command description the description of the various controller commands uses the following formalism: ? abbreviations used in the following descriptions: a address d data value n count value o offset value r register number x don ? t care ? a data value is split into 4-bit nibbles which are num- bered zero-bound. ? data values in nibbles are always shown in hexa- decimal notation. ? a hexadecimal 20-bit number d is written, e.g. as d = 17c63 hex , its five nibbles are d0 = 3 hex , d1 = 6 hex , d2 = c hex , d3 = 7 hex , and d4 = 1 hex . ? variables used in the following descriptions: dev_write 3a hex device write dev_read 3b hex device read data_write 68 hex data register write data_read 69 hex data register read control 6a hex control register write ? bus signals sstart pstop a ack = acknowledge n nak = not acknowledge ? symbols in the telegram examples < start condition > stop condition dd data byte xx ignore all telegram numbers are hexadecimal, data origi- nating from the mas 3528e are shown in gray. example: <3a 68 dd dd> write data to dsp <3a 69 <3b dd dd > read data from dsp fig. 3 ? 1 shows i 2 c bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with the read command (3b hex ). fields with signals/data originating from the mas 3528e are marked by a gray background. note that in some cases, the data reading process must be concluded by a nak condition. table 3 ? 1: i 2 c device address a7 a6 a5 a4 a3 a2 a1 w/r 00111010/1 table 3 ? 2: subaddresses sub- address i 2 c- register function 68 hex data controller writes to mas 3528e data register 69 hex data controller reads from mas 3528e data register 6a hex control controller writes to mas 3528e control register
mas 3528e advance information 18 micronas fig. 3 ? 1: i 2 c bus protocol for the mas 3528e (msb first; data must be stable while clock is high) 3.2.4. the internal fixed point number format in the following sections, two number representations are used: the fixed point notation ? v ? and the 2 ? s com- plement number notation ? r ? . the conversion between the two forms of notation is easily done (see the following equations). r = v*524288.0+0.5; ( ? 1.0 v < 1.0) (eq 1) v = r/524288.0; ( ? 524288 < r < 524287) (eq 2) 3.3. i 2 c control register (subaddress 6a hex ) l the i 2 c control register is a write-only register. its main purpose is the software reset of the mas 3528e. the software reset is done by writing a 16-bit word to the mas 3528e with bit 8 set. the four least significant bits are reserved for task selection. the task selection is only useful in combination with download software. in standard dolby digital/mpeg-decoding, these bits must always be set to 0. 3.4. i 2 c data register (subaddresses 68 hex and 69 hex ) and the mas 3528e dsp-command syntax the dsp-core of the mas 3528e has two ram-banks denoted d0 and d1. the word size is 20 bits. all ram- addresses can be accessed in a 20-bit or a 16-bit mode via i 2 c-bus. for fast access of internal dsp- states, the processor core also has an address space of 256 data registers. all register and ram-addresses are given in hexadecimal notation. the control of the dsp in the mas 3528e is done via the i 2 c data register by using a special command syn- tax. these commands allow the controller to access the dsp-registers and ram-cells and thus monitor internal states, set the parameters for the dsp-firm- ware, control the hardware, and even provide a down- load of alternative software modules. the dsp-commands consist of a ? code ? which is sent to i 2 c-data register together with additional parame- ters. the mas 3528e firmware scans the i 2 c interface peri- odically and checks for pending or new commands. the commands are then executed by the dsp during its normal operation without any loss or interruption of the incoming data or outgoing audio data stream. how- ever, due to some time critical firmware parts, a certain latency time for the response has to be expected. the theoretical worst case response time does not exceed 4 ms. however, the typical response time is less than 0.5 ms. table 3 ? 4 on page 19 shows the basic control- ler commands that are available by the mas 3528e. s a high data word low data word high data word s dev_write (3a hex ) a a a n p example: i 2 c write access i 2 c read access sda scl 1 0 s p start stop a n s p = = = = 0 (ack) 1 (nak) data_write (68 hex ) p a dev_read (3b hex ) example: s dev_write (3a hex ) a data_read (69 hex ) a a low data word table 3 ? 3: control register bit assignment1) 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 xxxxxxxr0000t3t2t1t0 1) x = don ? t care, r = reset, t3...t0 0 task selection ap d1,d0 a a a s dev_write control d3,d2 a a sa dev_write data_write code, ... ..., ... ... a
advance information mas 3528e micronas 19 ta b l e 3 ? 4 gives an overview of the different commands which the dsp-core may receive. the ? code ? is always the first data nibble transmitted after the ? data_write ? byte. a second auxiliary code nibble is used for the short memory access commands. because of the 16-bit width of the i 2 c-data register, all actions always transmit telegrams with multiples of 16 data bits. 3.4.1. run and freeze the run command causes the start of a program part at address a = (a3,a2,a1,a0). since nibble a3 is also the command code (see table 3 ? 4), it is restricted to values between 0 and 3. if the start address is 1000 hex a < 1fff hex and the respective ram area has been configured as program ram (see table 3 ? 5 on page 23), the mas 3528e continues execution with a custom program already downloaded to this area (see section 2.5.1. on page 9). example 1: start program execution at address 345 hex : <3a 68 03 45> example 2: start execution of a downloaded code at address 1000 hex : <3a 68 10 00> freeze is a special run command with start address 0. it suspends all normal program execution. the operat- ing system will enter an idle loop so that all registers and memory cells can be watched. this state is useful for operations like downloading code or contents of memory cells because the internal program cannot overwrite these values. this freezing will be required if alternative software is downloaded into the internal ram of the mas 3528e (see section 2.5.1. on page 9). freeze has the following i 2 c protocol: <3a 68 00 00> the entry point of the default software will be accessed automatically. thus issuing a run or freeze command is only necessary for starting downloaded software or special program modules which are not part of the standard set. table 3 ? 4: basic controller command codes code (hex) command function 0 ... 3 run start execution of an internal program. run with start address 0 hex means freeze the operating system a read from register controller reads an internal register of the mas 3528e. b write to register controller writes an internal register of the mas 3528e. c read d0 memory controller reads a block of the dsp memory. d read d1 memory controller reads a block of the dsp memory. e write d0 memory controller writes a block of the dsp memory. f write d1 memory controller writes a block of the dsp memory. s a aaap dev_write data_write a3 ,a2 a1,a0
mas 3528e advance information 20 micronas 3.4.2. read register the mas 3528e has an address space of 256 dsp- registers. some of the registers ( r = r1,r0 in the figure above) are direct control inputs for various hardware blocks, others control the internal program flow. in sec- tion 3.5. on page 23, the registers of interest with respect to the dolby digital/mpeg-decoding firmware are described in detail. in contrast to memory cells, registers cannot be accessed as a block but must always be addressed individually. example: read the content of register (2e hex ): <3a 68 a2 e0> define register <3a 69 <3b xx xd dd dd > and read 3.4.3. write register the controller writes the 20-bit value ( d = d4,d3,d2,d1,d0) into the mas 3528e register ( r = r1,r0). a list of registers is given in section 3.5. on page 23 example: disable automatic s/pdif loop-through for dts by writing the value 1000 hex into the register with the number 2e hex : <3a 68 b2 e0 10 00> 3.4.4. read d0 memory the mas 3528e has 2 memory areas called d0 and d1. both areas have different read and write com- mands. the read d0 memory command gives the controller access to all 20 bits of d0-memory cells of the mas 3528e. the telegram to read three words starting at location d0:100 hex is <3a 68 c0 00 00 03 01 00> <3a 69 <3b xx xd dd dd xx xd dd dd xx xd dd dd > 3.4.5. short read d0 memory because most cells in the dolby digital user interface are only 16 bits wide, it is faster and more convenient to access the memory locations with a special 16-bit mode for reading: this command is similar to the normal 20-bit read command and uses the same command codes c hex , however, this nibble is followed by a 4 hex rather than a 0 hex . 1) send command 2) get register value saaaap saasa np a a a dev_write dev_write data_write data_read dev_read x,x x,d4 d3,d2 d1,d0 $a ,r1 r0,$0 saaa a a ap d1,d0 r0,d4 $b ,r1 d3,d2 data_write dev_write 1) send command 2) read memory ... repeat for n data values ... saaaa a aa a p saasa aaaa aaanp dev_write data_write $c ,$0 $0,$0 n3,n2 n1,n0 a3,a2 a1,a0 dev_write data_write dev_read x,x x,x x,d4 x,d4 d3,d2 d3,d2 d1,d0 d1,d0 1) send command 2) read memory ... repeat for n data values ... s a aaa aa aap saasa aa anp dev_write data_write $c,$4 $0,$0 n3,n2 n1,n0 a3,a2 a1,a0 dev_write data_read dev_read d3,d2 d1,d0 d3,d2 d1,d0
advance information mas 3528e micronas 21 3.4.6. read d1 memory the read d1 memory command is provided to get information from d1 memory cells of the mas 3528e. 3.4.7. short read d1 memory the short read d1 memory command works similarly to the read d1 memory command but with the code d hex followed by a 4 hex . example: read 16 bits of d1:123 has the following i 2 c protocol: <3a 68 d4 00 read 16 bits from d1 00 01 one word to be read 01 23> start address <3a 69 <3b dd dd > start reading 3.4.8. write d0 memory with the write d0 memory command n 20-bit memory cells in d0 can be initialized with new data. example: write 80234 hex to d0:ffb hex has the follow- ing i 2 c protocol: <3a 68 e0 00 write d0 memory 00 01 1 word to write 0f fb start address ffb hex 00 08 value = 80234 hex 02 34> 3.4.9. short write d0 memory for faster access, only the lower 16 bits of each mem- ory cell are accessed. the four msbs of the cell are cleared. the code combination is e4 hex . 3.4.10.write d1 memory for further details, see the write d0 memory com- mand. 1) send command 2) read memory ... repeat for n data values ... saaaa a aa a p saasa aaaa aaanp dev_write data_write $d ,$0 $0,$0 n3,n2 n1,n0 a3,a2 a1,a0 dev_write data_write dev_read x,x x,x x,d4 x,d4 d3,d2 d3,d2 d1,d0 d1,d0 1) send command 2) read memory ... repeat for n data values ... s a aaa aa aap saasa aa anp dev_write data_write $d,$4 $0,$0 n3,n2 n1,n0 a3,a2 a1,a0 dev_write data_read dev_read d3,d2 d1,d0 d3,d2 d1,d0 ... repeat for n data values ... s a aaa aa aa aa aa aa aap dev_write data_write $e ,$0 $0,$0 n3,n2 n1,n0 a3,a2 a1,a0 0,0 0,d4 d3,d2 d1,d0 0,0 0,d4 d3,d2 d1,d0 ... repeat for n data values ... s a aaa aa aa aa aap dev_write data_write $e , $4 $0,$0 n3,n2 n1,n0 a3,a2 a1,a0 d3,d2 d1,d0 d3,d2 d1,d0 ... repeat for n data values ... s a aaa aa aa aa aa aa aap dev_write data_write $f ,$0 $0,$0 n3,n2 n1,n0 a3,a2 a1,a0 0,0 0,d4 d3,d2 d1,d0 0,0 0,d4 d3,d2 d1,d0
mas 3528e advance information 22 micronas 3.4.11.short write d1 memory only the 16 lower bits of each memory cell are written, the upper four bits are cleared. 3.4.12.default read the default read command is the fastest way to get information from the mas 3528e. executing the default read in a polling loop can be used to detect a special state during decoding. the default read command immediately returns the lower 16 bit content of a specific ram location as defined by the pointer d0:ffb hex . the pointer must be loaded before the first default read action occurs. if the msb of the pointer is set, it points to a memory location in d1 rather than to one in d0. example: for watching d1:123, the pointer d0:ffb must be loaded with 8123 hex : <3a 68 e0 00 write to d0 memory 00 01 one word to write 0f fb start address ffb 00 08 value = 8 hex ... 01 23> ...0123 hex now the default read commands can be issued as often as desired: <3a 69 <3b default read command dd dd > 16 bit content of the address as defined by the pointer <3a 69 <3b dd dd > ... and do it again ... repeat for n data values ... saaaa aa aa aa aap dev_write data_write $f , $4 $0,$0 n3,n2 n1,n0 a3,a2 a1,a0 d3,d2 d1,d0 d3,d2 d1,d0 saasa anp dev_write data_read device_read d3,d2 d1,d0
advance information mas 3528e micronas 23 3.5. registers in table 3 ? 5, the internal registers that are useful for controlling the mas 3528e are listed. they are accessible by read/write register i 2 c commands (see section 3.4.2. and section 3.4.3. on page 20). note: registers not given in this table must not be written. table 3 ? 5: command register table register address (hex) r/w function default (hex) name 2e r/w loop-through and sync pin controlling bit[12] 0: automatic active loop-through if dts is recognized or the input format at s/pdif_in cannot be determined (default) 1: bit[1] controls loop-through bit[11:2] reserved: do not change! bit[1] 0: normal operation 1: connect spdi_in to spdif out (loop-through) bit[0] sync bit (will be automatically detected and set by internal software) 00000 output_conf 56 r incoming s/pdif channel status bits bit[19:0] mirrors first 20 channel status bits spi0cs
mas 3528e advance information 24 micronas 3.6. special memory locations and user interface operation of the dsp and the interfaces can be observed and controlled via the memory locations of the user inter- face. these memory cells are located at the high end of the d0-ram. status cells are written by the dsp and read by the controller, configuration cells are written by the controller and read by the dsp, hybrid cells can be written and read by either side. note: memory addresses not given in this table must not be accessed. 3.6.1. status interface for decoding the following table contains the memory locations of the firmware status information. addresses are hexadecimal, memory cell content is binary when written without indicator and hexadecimal when written with a hex-suffix. table 3 ? 6: status memory cells memory address (hex) function mode name d0:13a0 ac-3 sample rate codes (fscod) dolby digital (table 5.1 of atsc spec. a/52) bit[1:0] 00 48 khz 01 44.1 khz 10 32 khz 11 not detected (default) ac-3 sample rate as included in the bit stream. uis_fscod d0:13a1 bit stream identification (bsid) dolby digital (section 5.4.2.1 of atsc spec. a/52) bit[4:0] 00 hex ...1f hex current bsid value bit streams that have a bsid higher than the decoder ? s version number may be incompatible. in this case, the decoding is inhibited. the version number for the implemented firmware is 8. uis_bsid d0:13a2 bit stream mode (bsmod) dolby digital (table 5.2 of atsc spec. a/52) bit[2:0] 000 main audio service: complete main (cm) 001 main audio service: music and effects (me) 010 associated service: visually impaired (vi) 011 associated service: hearing impaired (hi) 100 associated service: dialogue (d) 101 associated service: commentary (c) 110 associated service: emergency (e) 111 acmod = 001, associated service: voice over (vo) 111 acmod = 010-111, main audio service: karaoke this information is valid after selecting (d0:13d0) an available (d0:13bc) channel (data stream) from the s/pdif-input. prior to this, the bsmod can be directly derived from the pc-preambles of the s/pdif-data (d0:13bd...13c4). uis_bsmod
advance information mas 3528e micronas 25 d0:13a3 audio coding mode (acmod) dolby digital (table 5.3 of atsc spec. a/52) bsmod != ? 111 ? bsmod = ? 111 ? (karaoke) bit[2:0] 000 1+1 ch1, ch2 voice over (vo) 001 1/0 c 010 2/0 l, r l, r 011 3/0 l, c, r l, m, r 100 2/1 l, r, s l, r, v1 101 3/1 l, c, r, s l, m, r, v1 110 2/2 l, r, sl, sr l, r, v1, v2 111 3/2 l, c, r, sl, sr l, m, r, v1, v2 for user information: indicates the applied main channel. uis_acmod d0:13a4 center mix level (cmixlev) dolby digital (table 5.4 of atsc spec. a/52) bit[1:0] 00 0.707 ( ? 3.0 db) 01 0.595 ( ? 4.5 db) 10 0.500 ( ? 6.0 db) 11 reserved ( ? 6.0 db), nominal downmix level of center with respect to left and right channels used in the internal algorithm. uis_clev d0:13a5 surround mix level (surmixlev) dolby digital (table 5.5 of atsc spec. a/52 ) bit[1:0] 00 0.707 ( ? 3.0 db) 01 0.500 ( ? 6.0 db) 10 0 11 reserved ( ? 6.0 db), nominal downmix level of surround channels used in the internal algorithm. uis_slev d0:13a6 dolby surround mode (dsurmod) dolby digital (table 5.6 of atsc spec. a/52) bit[1:0] 00 not indicated 01 not dolby surround encoded 10 dolby surround encoded 11 reserved (not indicated) as soon as the audio is dolby surround encoded, the controller must activate the dolby pro logic decoder (e.g. in the dpl 4519g) without any user interac- tion. uis_dsurmod d0:13a7 low frequency effects channel (lfeon) dolby digital (section 5.4.2.7 of atsc spec. a/52) bit[0] 0 lfe off 1lfe on the user may want to choose a different output configuration depending on the availability of the lfe. uis_lfeon table 3 ? 6: status memory cells memory address (hex) function mode name
mas 3528e advance information 26 micronas d0:13a8 dialogue nomalization (dialnorm) dolby digital (section 5.4.2.8 of atsc spec. a/52) bit[4:0] 01 hex ... average dialog level ? 1 db... ? 31 db below 1f hex 100% digital 00 hex reserved used in the internal algorithm. uis_dialnorm d0:13aa language code (langcode, langcod) dolby digital (sections 5.4.2.11 and 5.4.2.12 of atsc spec. a/52) bit[15:0] ffff hex langcode = 0 (langcod nonexistent in stream) bit[7:0] langcod the controller may check all s/pdif-data streams (channels) for the desired language. uis_langcod d0:13ab mixing level and room type dolby digital (audprodie, mixlevel, roomtyp) (sections 5.4.2.13, 5.4.2.14 and 5.4.2.15 of atsc spec. a/52) bit[15:0] ffff hex audprodie = 0 (mixlevel, roomtyp nonexistent in data stream) bit[6:2] mixlevel bit[1:0] roomtyp for user information. uis_mixlevel_ roomtyp d0:13ac dialogue nomalization 2 for dual mono mode 1+1 dolby digital (dialnorm2) (section 5.4.2.16 of atsc spec. a/52) bit[4:0] 01 hex ...1f hex average dialog level ? 1db... ? 31db below 100% digital 00 hex reserved used in the internal algorithm. uis_dialnorm2 d0:13ae language code 2 for ch2 in dolby digital dual mono mode 1+1 (langcod2e, langcod2) (section 5.4.2.19 and 20 of atsc spec. a/52) bit[15:0] ffff hex langcod2e = 0 (langcod2 nonexistent in stream) bit[7:0] langcod2 used in the internal algorithm. uis_langcod2 d0:13af mixing level and room type for ch2 in dolby digital dual mono mode 1+1 (audprodi2e, mixlevel2, roomtyp2) (section 5.4.2.21, 22 and 23 of atsc spec. a/52) bit[15:0] ffff hex audprodi2e = 0 (mixlevel2, roomtyp2 nonexistent in stream) bit[6:2] mixlevel2 bit[1:0] roomtyp2 for user information. uis_mixlevel2_ roomtyp2 table 3 ? 6: status memory cells memory address (hex) function mode name
advance information mas 3528e micronas 27 d0:13b0 copyright bit (copyrightb) dolby digital (section 5.4.2.24of atsc spec. a/52) bit[0] 0 not protected 1 protected by copyright uis_copyright b d0:13b1 original bit stream (origbs) dolby digital (section 5.4.2.25 of atsc spec. a/52) bit[0] 0 copy of a bit stream 1 original bit stream uis_origbs d0:13b2 time code 1 dolby digital (section 5.4.2.27of atsc spec. a/52) bit[15:0] ffff hex timecod1e = 0 (time code 1 nonexistent) bit[13:0] time code 1(first half) bit[13:9] time in hours (0...23 valid) bit[8:3] time in minutes (0...59 valid) bit[2:0] time in 8-second increments (0 = 0 seconds) (1 = 8 seconds) : (7 = 56 seconds) for external synchronization purposes. uis_timecod1 d0:13b3 time code 2 dolby digital (section 5.4.2.28of atsc spec. a/52) bit[15:0] ffff hex timecod2e = 0 (time code 2 nonexistent) bit[13:0] time code 2 (second half) bit[13:11] time in 8-second increments, see time code 1 bit[10:6] time in frames (0...29 valid) bit[5:0] time in 1/6 frames for external synchronization purposes. uis_timecod2 d0:13b4 dynamic range gain word (dynrnge, dynrng) dolby digital (section 5.4.3.3 and 5.4.3.4 of atsc spec. a/52) bit[15:0] ffff hex dynrnge = 0 (dynrng nonexistent in stream) bit[7:0] current dynrng value used in the internal algorithm. uis_dynrng d0:13b5 dynamic range gain word 2 for ch2 in dolby digital dual mono mode (dynrng2e, dynrng2) (section 5.4.3.5 and 5.4.3.6 of atsc spec. a/52) bit[15:0] ffff hex dynrng2e = 0 (dynrng2 nonexistent in stream) bit[7:0] current dynrng value used in the internal algorithm. uis_dynrng2 table 3 ? 6: status memory cells memory address (hex) function mode name
mas 3528e advance information 28 micronas d0:13b6 karaoke flag dolby digital bit[0] 0 no karaoke info in bit stream 1 karaoke info in bit stream uis_ karaokeflag d0:13b7 frame count dolby digital, mpeg bit[19:0] counts 0, 1, 2, 3, 4, ..., 1048575 (= fffff hex ), 1, ... uis_frame_ counter d0:13b8 mpeg header bits 12...31 mpeg bit[19] id (must be 1 for mpeg-1) bit[18:17] layer 00 reserved 01 layer 3 10 layer 2 11 layer 1 bit[16] protection 0 crc 1 no crc bit[15:12] bit rate (see table in iec 11172-3, layer 2) 0 hex free 132 248 356 464 580 696 7112 8128 9160 a192 b224 c256 d320 e384 f forbidden bit[11:10] sampling frequency (mpeg-1 layer-2) 00 44.1 khz 01 48 khz 10 32 khz 11 reserved ... uis_mpeg_ header table 3 ? 6: status memory cells memory address (hex) function mode name
advance information mas 3528e micronas 29 d0:13b8 (continued) bit[9] padding bit bit[8] private bit bit[7:6] mode 00 stereo 01 joint stereo 10 dual channel 11 reserved bit[5] joint stereo mode extension ms_stereo 0off 1on bit[4] joint stereo mode extension intensity stereo 0off 1on bit[3] copyright 0 not protected 1protected bit[2] original/copy 0copy 1original bit[1:0] emphasis 00 none 01 50/15 s 10 reserved 11 ccitt j.17 d0:13b9 mpeg status mpeg bit[5] 0 mono 1stereo bit[4] 1 crc error bit[3:2] >0 other decoding error (not enough data) bit[1:0] >0 header error uis_mpeg_ status table 3 ? 6: status memory cells memory address (hex) function mode name
mas 3528e advance information 30 micronas d0:13bb global operation status (gos) s/pdif-input bit[7:5] gos_type 0 gos_nodec, not decodable 1 gos_pcm_warn, channel status not plausible 2 gos_data, data type 3 gos_pcm 4...6 reserved 7 gos_i2s bit[4:1] appl_type 0ac-3 1 mpeg layer-2 2pcm 3time code 4 noise generator 5dts 15 unknown bit[0] 0 unsynchronized (default) 1 valid bit stream detected this status cell reflects the result of the decoding with the parameters given. if an incorrect input data type (d0:13d0) is selected, the input data stream will not be decodable. the gos_pcm_warn-flag is set when the s/pdif-channel status indicates pcm-encoded audio, but valid synchronization headers (dolby digital or mpeg) are found. uis_gos d0:13bc bit stream information s/pdif-input each bit: 1 channel available 0 channel not available bit[7] bit stream number 7 ... bit[0] bit stream number 0 available bit streams (channels) in the s/pdif-data. uis_dsi table 3 ? 6: status memory cells memory address (hex) function mode name
advance information mas 3528e micronas 31 d0:13bd ... d0:13c4 pc information of selected data stream (burst_info) s/pdif-input (section 4.4.3 of annex b of atsc spec. a/52) bit[15:13] 0 hex ...7 hex channel number (data_stream_number) bit[12:8] data_type_dependent, see below bit[7] error flag (error_flag) 0 data may be valid 1 data burst may contain errors bit[6:5] reserved bit[4:0] 00 hex reserved 01 hex ac-3 data 02 hex reserved 03 hex pause 04 hex mpeg layer-1 05 hex mpeg-1 layer-2, 3, or mpeg-2 without extension 06 hex mpeg-2 data with extension 07 hex reserved 08 hex mpeg-2 layer-1 low fs 09 hex mpeg-1 layer-2, 3 low fs 0a hex reserved 0b hex. ...d hex. dts 0e hex. ...1f hex. reserved this memory cell mirrors the pc-word of the s/pdif-preamble (burst_info) of the selected of eight possible data streams (channels) if available. uis_pc, i = 0...7 meaning of field data_type_dependent dolby digital ac-3: (section 4.7 of annex b of atsc spec. a/52) bit[12,11] 00 reserved, shall be ? 00 ? bit[10:8] value of bsmod as described in d0:13a2: 01 hex 02 hex 03 hex ...1f hex reserved d0:13c7 s/pdif status s/pdif bit[5:2] reserved bit[1] data mode 0pcm 1 compressed audio data bit[0] s/pdif copy active 0inactive 1active uis_sp_status d0:1fff version number all returns the version number of the rom-code as ascii uis_version table 3 ? 6: status memory cells memory address (hex) function mode name
mas 3528e advance information 32 micronas 3.6.2. control interface for decoding operation the following table gives the writable memory addresses of the control interface for the decoding firmware. table 3 ? 7: configuration memory cells memory address (hex) function mode reset value (hex) name d0:13d0 i/o control 00000 uic_io_contro l soft mute all bit[15] soft mute 0 soft mute off 1 soft mute on this switch is provided for user-controlled fast audio mute. crc check dolby digital mpeg bit[14] crc1 0 crc1 on 1 crc1 off bit[13] crc2 0 crc2 on 1 crc2 off dolby digital: crc1 protects the header and 3/5 of the data, crc2 protects the remaining 2/5 of the data. it is recommended that both ac-3 crc- checks are enabled which yields to an automatic mute upon detec- tion of an error. however, under special operating conditions (noisy channel), it may be advantageous to turn one (preferably crc2) or both crc-checks off. in this case, it is important to decrease the lis- tening volume to prevent hearing injuries and damages to the equip- ment. mpeg: for mpeg, only crc1 is applied. it is recommended to enable crc1 to avoid strong digital noise in case of deranged or unreliable signals. s/pdif channel select s/pdif bit[12:10] s/pdif channel select 000 channel 0 ... 111 channel 7 the s/pdif may carry up to eight channels of compressed audio. their content is shown in the s/pdif-pc-preambles (d0:13b8...13bf).
advance information mas 3528e micronas 33 d0:13d0 input and mode selection all bit[9] s/pdif or i 2 s input select 0 s/pdif input 1i 2 s input bit[8] i 2 s input select 0i 2 s input at sid (word mode) 1 continuos data stream at sid (sii connected to ground) bit[7:6] input data type 00 auto-detection 01 ac-3 (dolby digital) 10 mpeg layer-2 11 pcm 00000 uic_io_contro l output interface mode all bit[1] i 2 s output channels 08 1 channels 14 2 channels the clock and word strobe outputs soc and soi apply to all 4 data outputs sod...sod3 bit[0] i 2 s output mode 0 sony mode 1 philips mode d0:13d1 noise generator all (sec. 4.10.2 of dolby digital licensee information manual issue 3) bit[7] 0 noise generator off 1 noise generator on bit[6] noise type 0 white noise 1 band-pass shaped noise bit[5:0] 000001 l 000010 c 000100 r 001000 ls 010000 rs 100000 lfe 000000 no channel selected by combining the appropriate bits, more than one channel can out- put noise. the noise type can be selected between white and band- pass filtered with a maximum between 500 and 1000 hz. the required stepping actions have to be initiated by the controller. 00000 uic_noise d0:13d2 center channel delay dolby digital (sec. 4.10.1 of dolby digital licensee information manual issue 3) bit [2:0] 000 0 ms ... 101 5 ms 00000 uic_c_delay table 3 ? 7: configuration memory cells memory address (hex) function mode reset value (hex) name
mas 3528e advance information 34 micronas d0:13d3 left surround channel delay dolby digital (sec. 4.10.1 of dolby digital licensee information manual issue 3) bit[3:0] 0000 0 ms ... 1111 15 ms the surround delay for dolby pro logic decoded signals must be set in the dpl 4519g. 00001 uic_sl_delay d0:13d4 right surround channel delay dolby digital (sec. 4.10.1 of dolby digital licensee information manual issue 3) bit[3:0] 0000 0 ms ... 1111 15 ms the surround delay for dolby pro logic decoded signals must be set in the dpl 4519g. 00000 uic_sr_delay d0:13d5 lfe channel enable dolby digital bit[0] route lfe channel to subwoofer output (if it exists in stream) 1 enable lfe 0 disable lfe the subwoofer output is assembled from the lfe and the other channels depending on the output configuration. this switch dis- ables only content coming from the lfe. 00001 uic_out_lfe table 3 ? 7: configuration memory cells memory address (hex) function mode reset value (hex) name
advance information mas 3528e micronas 35 d0:13d6 output mode control (downmixing) dolby digital (section7.8 of atsc spec. a/52) bit[5:4] dual mono setting of dolby c decoder, applicable only if audio coding mode is dual mono (acmod = 0). the actual mixing depends on the number of available output channels (speakers). 00 stereo (straight output of both channels) 01 left mono (channel 1) 10 right mono (channel 2) 11 mixed mono (sum of both channels) bit[2:0] listening mode selector defines the number of available (desired) output channels (loudspeakers). 000 2/0 l, r dolby surround compatible 001 1/0 c 010 2/0 l, r 011 3/0 l, c, r 100 2/1 l, r, s 101 3/1 l, c, r, s 110 2/2 l, r, sl, sr 111 3/2 l, c, r, sl, sr these downmixing options are independent of the setting of the headphone output (d0:13de). undesired channels can be muted by setting the volume to zero or by muting the outputs in the dpl 4519g or msp 4450g, respec- tively. 00007 uic_out_mode_ control d0:13d7 compression control dolby digital (operational modes, dialog normalization) (sec. 3.7 of dolby digital licensee information manual issue 3) bit[1:0] setting of dolby c decoder 00 custom mode 0 (analog dialog normalization) 01 custom mode 1 (internal digital dialog normalization) 10 line mode 11 compression rf out the implemented dynamic range compression uses the transmitted variables dynrng, compr, and dialnorm. in line mode and in the custom modes, the dynamic compression may be scaled down by using the user-controlled high-level cut and low-level boost factors. note that in custom mode 0, the effect of dynrng must be imple- mented in the analog part of the audio equipment. note that in the custom mode downmix, an internal digital attenua- tion of 11 db is applied that must be compensated externally. 00001 uic_ compression_ control table 3 ? 7: configuration memory cells memory address (hex) function mode reset value (hex) name
mas 3528e advance information 36 micronas d0:13d8 high-level cut compression scale factor dolby digital (sec. 3.7 and sec. 4.11.9 of dolby digital licensee information manual issue 3) bit[19:0] 00000 hex (full dynamic)...7ffff hex (full compression) this factor scales down potential attenuation (i.e. dynamic compres- sion) of loud portions of the audio as defined by dynrng. high-level cut is only used in line mode (except in downmix) and in the cus- tom modes. note: in order to prevent clipping due to the downmixing in the cus- tom and line modes, the high-level cut compression scale factor must always be left at 7ffff hex when the two supplementary down- mix outputs (d0:13de) are used in conjunction with non-downmixed channels (d0:13d6). please refer to section 4.5.8. of dolby digital licensee information manual issue 3 7ffff uic_cut_x d0:13d9 low-level boost compression boost factor dolby digital (sec. 3.7 and sec. 4.11.9 of dolby digital licensee information manual issue 3) bit[19:0] 00000 hex (full dynamic)...7ffff hex (full compression) this factor scales down potential amplification (i.e. dynamic com- pression) of weak portions of the audio as defined by dynrng. low- level boost is only used in line mode and in the custom modes. 7ffff uic_boost_y d0:13da bass management all (see chapter 2.9.10.3.;sec. 4.7 of dolby digital licensee information manual issue 3) bit[4:0] 0000 direct loop-through of all six channels without channel mixing 1000 dolby configuration 0 1001 dolby configuration 1 1010 dolby configuration 2 1011 dolby alternative configuration 2 1100 dolby configuration 3 (no subwoofer out) 1101 dolby configuration 3 (subwoofer out) 1110 dvd configuration (bass to l/r) 1111 dvd configuration (bass to subwoofer) note: if bass management is enabled, high processor clock must be selected (d0:13df; bit16 = 1) the lfe-content can be disabled in d0:13d5. the output configurations can be used for all input formats. how- ever, for mpeg and pcm-dat, only the l and r input channels will carry information. 00000 uic_post_ processing table 3 ? 7: configuration memory cells memory address (hex) function mode reset value (hex) name
advance information mas 3528e micronas 37 d0:13db sampling frequency pcm at i 2 s-input bit[1:0] 00 48 khz 01 44.1 khz 10 32 khz the sampling frequency code is to be set by the controller in case of pcm-input at the i 2 s-interface. 00000 uic_samp_freq d0:13dd karaoke mode dolby digital bit[1:0] 00 no vocals 01 vocal 1 10 vocal 2 11 vocal 1 (left) + vocal 2 (right) 00003 uic_karaoke_ mode d0:13de lt/rt and lo/ro stereo output dolby digital (surround encoded) bit[0] 0 lt/rt stereo output 1 lo/ro stereo output for headphone operation, the 2-channel output can be switched to the lo/ro-mode. note: in order to prevent clipping due to the downmixing in the cus- tom and line modes, the high-level cut compression scale factor (d0:13d8) must always be left at 7ffff hex when the downmix out- puts are used in conjunction with non-downmixed channels (d0:13d6). 00000 uic_downmix_ mode table 3 ? 7: configuration memory cells memory address (hex) function mode reset value (hex) name
mas 3528e advance information 38 micronas d0:13df output clock scaling all bit[19] clko off 0 enable clko 1 disable clko bit[18:17] division factor applied to the internal reference clock (see table 2 ? 2 on page 9) for the clko-output 0 divide reference clock by 1 1 divide by 2 2 divide by 4 3 divide by 8 bit[16] low/high system clock for dolby digital (please refer to table 2 ? 1 on page 9) 0 61/56/40 mhz for 48/44.1/32 khz 1 73/67/49 mhz for 48/44.1/32 khz sets the processor clock and the output clock at pin clko. the clock frequencies are coupled to the audio data sampling rate of the input signal by a pll. 80004 uic_out_clk_ scale auxiliary interface control all bit[6] s/pdif input select 0 select spdi input 1 select spdi2 input bit[5] 0 reserved (set to 0) bit[4] disable sdi input 0sdi on 1sdi off bit[3] disable sdo output 0sdo on 1 sdo off pio [2:0] bit[2] soc impedance 0 low impedance 1 high impedance bit[1] serial input select 0 select sid, sii, sic 1 select sid*, sii*, sic* bit[0] 0 reserved input/output interface selections. table 3 ? 7: configuration memory cells memory address (hex) function mode reset value (hex) name
advance information mas 3528e micronas 39 d0:13e0 pcm/mpeg deemphasis control mpeg/pcm bit[1:0] deemphasis 00 automatic detection (only for pcm via s/pdif and all mpeg-inputs, no deem- phasis if pcm via i 2 s-input is selected) 01 50/15 s deemphasis 10 no deemphasis 11 j17 deemphasis pcm-signals coming via the serial interface do not contain embed- ded deemphasis information. the correct deemphasis must there- fore be initiated by the controller. pcm-signals coming via the s/pdif-interface and mpeg-data streams contain such information. in this case, the automatic detec- tion should be enabled to achieve the correct deemphasis. 00000 uic_deemphase _control d0:13e1 d0:13e2 d0:13e3 d0:13e4 d0:13e5 d0:13e6 d0:13e7 d0:13e8 volume control all volume left channel volume right channel volume surround left channel volume surround right channel volume center channel volume subwoofer channel volume stereo left channel volume stereo right channel bit[15:8] 7f hex +12 db ... 73 hex 0db ... 01 hex ? 114 db 00 hex mute the resolution is 1 db/step. 07300 (all) uic_l_volume uic_r_volume uic_sl_volume uic_sr_volume uic_c_volume uic_lfe_volum e uic_l_st_volum e uic_r_st_volu me d0:13ea bit[15:0] first 16 s/pdif all channel status bits (output) bit[15] l-bit (generation status) bit[8:14] category code bit[6:7] should be ? 0 ? bit[3:5] should be ? 0 ? bit[2] cp-bit (copyright protection) bit[1] should be ? 0 ? for pcm output bit[0] should be ? 0 ? for consumer use these bits are inactive if s/pdif loop-through is selected. note: please take care to set bits 2, 8 ... 15 correctly. incorrect settings may affect the ability to make digital copies. 01904 uic_channel _status table 3 ? 7: configuration memory cells memory address (hex) function mode reset value (hex) name
mas 3528e advance information 40 micronas 3.6.3. hybrid user interface cells table 3 ? 8: hybrid user interface cells memory address (hex) function reset value (hex) name d0:13ff error constants all messages bit[19:0] 0 no error 8 all errors with an error number higher or equal to this error number cause a restart 9 le_no_sync_init 10 le_no_sync_copy 11 data stream error (pa not correct) 12 data stream error (pb not correct) 13 data stream error (pc not correct) 14 data stream error (pd to big) 15 i2s timeout error 16 no input data type selected in i2s input mode (i.e. auto-detection is on) causes an error in the actual software version 17 input type over spdif changed from pcm to data 18 ac-3: initial waiting time out 19 ac-3: sync waiting time out 20 ac-3: sync lost 21 ac-3: header corrupted 22 ac-3: crc1 wait timeout 23 ac-3: crc1 fail 24 ac-3: crc2 wait timeout 25 ac-3: crc2 fail 26 selected bit-stream-number not available 27 pcm recognition inconsistent, restart 28 data type in burstinfo not ac-3, pcm, mpeg, or dts. 29 ac-3 - sampling frequency changed 30 invalid exponents detected 40 mpeg error 41 mpeg sampling frequency changed 42 mpeg: no header at expected position 43 mpeg: restart forced by controller 44 mpeg: not enough data to decode mpeg 50 le_user_change 51 le_io_control 52 le_noise 53 le_c_delay 54 le_sl_delay 55 le_rl_delay 56 le_out_lfe 57 le_out_mode_control 58 le_compression_control 59 le_cut_x 60 le_boost_y 61 le_post_processing 62 le_samp_freq 63 le_outn_channels 64 le_karaoke_mode 65 le_downmix_mode 66 le_out_clk_scale the latest error that occurred is displayed in this cell. the controller should frequently (e.g. once per frame) check and clear this memory location. 00000 uih_last_ error
advance information mas 3528e micronas 41 4. specifications 4.1. outline dimensions fig. 4 ? 1: 44-pin plastic leaded chip carrier package (plcc44k) weight approximately 2.5 g dimensions in mm 4.2. pin connections and short descriptions nc not connected, leave vacant lv if not used, leave vacant x obligatory, pin must be connected as described in application information vdd connect to positive supply vss connect to ground 15.7 0.3 10 x 1.27 = 12.7 0.1 1.2 x 45 140 39 29 28 18 17 7 6 1.6 0.1 6 8.6 6 2 2 x 45 1.1 1.27 1.27 spgs704000-1(p44/k)/1e 17.52 0.12 17.52 0.12 16.5 0.1 16.5 0.1 10 x 1.27 = 12.7 0.1 4.75 0.15 4.05 0.1 1.9 0.05 0.27 0.03 0.71 0.05 0.48 0.06 0.9 0.2 pin no. plcc 44-pin pin name type connection (if not used) short description 1 vss supply x ground supply for digital parts 2 vdd supply x positive supply for digital parts 3 i2cd in/out vdd i 2 c data line 4 i2cc in/out vdd i 2 c clock line 5por in x reset, active low 6 te in vss test enable 7 avss supply x ground supply for analog circuits 8 avdd supply x supply for analog circuits 9 xti in x clock input/quartz oscillator pin 1 10 xto out lv quartz oscillator pin 2 11 nc lv 12 nc lv
mas 3528e advance information 42 micronas 13 clko out lv dsp clock output for the d/a-converter 14 sod1 out lv serial output data 1 15 sod2 out lv serial output data 2 16 sod3 out lv serial output data 3 17 spdifout out lv s/pdif output 18 pi4 in/out lv pio data [4] 19 sic in vss serial input clock 20 sii in vss serial input frame identification 21 sid in vss serial input data 22 xvss supply x ground for output buffers 23 xvdd supply x positive supply for output buffers 24 pi8 in/out lv pio data [8] 25 soc out x serial output clock 26 soi out x serial output frame identification 27 sod out x serial output data 28 pi12 in/out lv pio data [12] 29 pi13 in/out lv pio data [13] 30 sid* (pi14) in/out lv pio data [14], sid* = alternative input for sid 31 sii* (pi15) in/out lv pio data [15], sii* = alternative input for sii 32 sic* (pi16) in/out lv pio data[16], sic* = alternative input for sic 33 pi17 in/out lv pio data [17] 34 pi18 in/out lv pio data [18] 35 pi19 in/out lv pio data [19] 36 pcs in vdd pio chip select, active low 37 pr in vdd pio dma request or read/write 38 spdi in vss s/pdif input 1 39 spref in lv s/pdif input (reference) 40 spdi2 in vss s/pdif input 2 41 rtw out lv pio ready to write, active low 42 rtr out lv pio ready to read, active low pin no. plcc 44-pin pin name type connection (if not used) short description
advance information mas 3528e micronas 43 4.3. pin descriptions 4.3.1. power supply pins connection of all power supply pins is mandatory for the functioning of the mas 3528e. vdd supply vss supply the vdd/vss pair is internally connected with all digi- tal modules of the mas 3528e. xvdd supply xvss supply the xvdd/xvss pins are internally connected with the pin output buffers. avdd supply avss supply the avdd/avss pair is connected internally with the analog blocks of the mas 3528e, i.e. clock synthesizer and supply voltage supervision circuits. 4.3.2. control lines i2cc scl in/out i2cd sda in/out standard i 2 c control lines. 4.3.3. parallel interface lines with the pr = ? 1 ? and the pcs = ? 0 ? , the pio interface is defined as output and displays some status informa- tion of the mpeg decoder. the pio can be connected to an external controller or to a display unit (e.g. led). the internal mpeg decoder firmware attaches specific functions to some of the pio-pins. pcs in the pio chip select must be set to ? 0 ? to activate the pio in operation mode. pr in pr must be set to ? 1 ? to validate pio data output from mas 3528e. rtr out rtr is not supported by the firmware. for detailed information, please refer to the masc software devel- opment kit. rtw out rtw is not supported by the firmware. eod out eod is not supported by the firmware. pi19 msb in/out pi18 in/out pi17 in/out pi16 in/out pi15 in/out pi14 in/out pi13 in/out pi12 lsb in/out data pin for parallel input/output interface. 4.3.4. clocking xti in this is the clock input of the mas 3528e. the nominal clock frequency is 18.432 mhz. xto in this connection is needed for the quartz oscillator. clko out the clko is an oversupplying clock that is synchro- nized to the digital audio data (sod) and the frame identification (soi). 4.3.5. serial input interface sid in sii in sic in data, frame indication, and clock line of the standard i 2 s (word mode) serial input interface. pi16 sic* in pi15 sii* in pi14 sid* in the sic*, sid*, and sii* are alternative serial input lines. this interface can be selected in memory cell d0:13d0. 43 eod out lv pio end of dma, active low 44 sync out lv reserved for frame synchronization pin no. plcc 44-pin pin name type connection (if not used) short description
mas 3528e advance information 44 micronas 4.3.6. s/pdif input interface spdi in spdi2 in spref in input lines (spdi/spdi2) and ground reference line (spref) of the s/pdif-input interfaces. one of the two alternate input lines is selected by in d0:13df. 4.3.7. s/pdif output interface spdifout out s/pdif-output line. 4.3.8. serial output interface sod out sod1 out sod2 out sod3 out soi out soc out data, frame indication, and clock line of the serial out- put interface. the soi indicates whether the left or the right audio sample is transmitted. besides the two modes, it is possible to reconfigure the interface. 4.3.9. miscellaneous por in the por pin is used to reset the digital parts of the mas 3528e. por is a low active signal. te in the te pin is for production test only and must be con- nected with vss in all applications. sync the sync pin is set while decoding dolby digital or mpeg. only during header processing, there is a short low period (20...300 s depending on the audio format) 4.4. pin configuration fig. 4 ? 2: 44-pin plcc package 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 avss avdd xti xto n.c. n.c. clko sod1 sod2 sod3 spdifout spref spdi pr pcs pi19 pi18 pi17 pi16 pi15 pi14 pi13 por i2cc i2cd vdd vss te sync eod rtr rtw spdi2 sic sii sid xvss xvdd pi4 pi8 soc soi sod pi12 mas 3528e
advance information mas 3528e micronas 45 4.5. internal pin circuits fig. 4 ? 3: input pins pcs , pr fig. 4 ? 4: input pin te fig. 4 ? 5: input pin por fig. 4 ? 6: clock oscillator xti, xto fig. 4 ? 7: input/output pins sod1, sod2, sod3, spdifout, pi4, pi8, soc, soi, sod, pi12...pi19 fig. 4 ? 8: input/output pins sic, sii, sid fig. 4 ? 9: input/output pins i2cc, i2cd fig. 4 ? 10: output pins rtw , eod , rtr , clko, sync fig. 4 ? 11: s/pdif input ttlin avdd avss p p p n n n xto xti enable vdd p n vss vdd p n vss vdd n vss vdd vss n p vdd bias ? + vdd spdi, spref spdi2
mas 3528e advance information 46 micronas 4.6. electrical characteristics 4.6.1. absolute maximum ratings stresses beyond those listed in the ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the ? recommended operating conditions/characteristics ? of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. symbol parameter pin name min. max. unit t a ambient operating temperature ? 20 70 c t s storage temperature ? 40 125 c p tot package power dissipation (plcc44k) vdd, xvdd, avdd 1250 mw v supd digital supply voltage vdd, xvdd ? 0.3 6.0 v v supa analog supply voltage avdd ? 0.3 6.0 v ? v sup voltage differences between any supply region (vdd, avdd, xvdd) vdd, avdd, xvdd ? 0.5 0.5 v v idig input voltage, all digital inputs ? 0.3 v sup +0.3 v i idig input current, all digital inputs ? 20 20 ma out current, all digital outputs 250 ma output load 300 pf
advance information mas 3528e micronas 47 4.6.2. recommended operating conditions (t a =0to+70 c) 4.6.2.1. general recommended operating conditions 4.6.2.2. reference frequency generation and crystal recommendations 4.6.2.3. input levels at v dd = 4.5 v...5.5 v symbol parameter pin name min. typ. max. unit v supd digital supply voltage vdd, xvdd 4.75 5.0 5.25 v v supa analog supply voltage avdd 4.75 5.0 5.25 v symbol parameter pin name min. typ. max. unit external clock input recommendations clk f clock frequency xti 18.432 mhz clk amp clock amplitude 0.7 3.5 v pp crystal recommendations t ac ambient temperature range xti, xto ? 20 80 c f p load resonance frequency at c i =12pf 18.432 mhz ? f/f s accuracy of frequency adjust- ment ? 50 50 ppm ? f/f s frequency variation vs. temper- ature ? 50 50 ppm r eq equivalent series resistance 12 30 ? c 0 shunt (parallel) capacitance 3 7 pf symbol parameter pin name min. typ. max. unit v il input low voltage por i2cc, i2cd 0.5 v v ih input high voltage 2.6 v v ild input low voltage pi, sii, sic, sid, pr, te, 0.5 v v ihd input high voltage v sup 0.5
mas 3528e advance information 48 micronas 4.6.3. characteristics at t a = 0 to 70 c, v dd = 5.0 v, f crystal = 18.432 mhz 4.6.3.1. general characteristics symbol parameter pin name min. typ. max. unit test conditions supply current i sup current consumption all supply pins 210 ma 5.0 v, audio sampling frequency 48 khz dolby digital, 61 mhz fproc digital outputs and inputs o digl output low voltage pi, soi, soc, sod, sod1, sod2, sod3, eod , rtr , rtw , clko spdif-out 0.3 v at i load =1ma o digh output high voltage v sup ? 0.3 vat i load =1ma c digi input capacitance all digital inputs 7pf i dleak input leakage current 1 a 0 v < v pin < v sup
advance information mas 3528e micronas 49 4.6.3.2. i 2 c characteristics fig. 4 ? 12: i 2 c timing diagram symbol parameter pin name min. typ. max. unit test conditions r on output resistance i2cc, i2cd 60 ? i load = 5 ma, v dd = 4.5 v f i2c i 2 c bus frequency i2cc 400 khz t i2c1 i 2 c start condition setup time i2cc, i2cd 300 ns t i2c2 i 2 c stop condition setup time i2cc, i2cd 300 ns t i2c3 i 2 c clock low pulse time i2cc 1250 ns t i2c4 i 2 c clock high pulse time i2cc 1250 ns t i2c5 i 2 c data hold time before rising edge of clock i2cc 80 ns t i2c6 i 2 c data hold time after falling edge of clock i2cc 80 ns v i2col i 2 c output low voltage i2cc, i2cd 0.3 v i load = 5 ma i i2coh i 2 c output high leakage current i2cc, i2cd 1av i2ch = 5.5 v t i2col1 i 2 c data output hold time after falling edge of clock i2cc, i2cd 20 ns t i2col2 i 2 c data output setup time before rising edge of clock i2cc, i2cd 250 ns f i2c = 400khz i2cc i2cd as input i2cd as output t i2c1 t i2c5 t i2c6 t i2c2 t i2c4 t i2c3 1/f i2c t i2col2 t ic2ol1 h l h l h l
mas 3528e advance information 50 micronas 4.6.3.3. s/pdif-bus input characteristics fig. 4 ? 13: timing of the s/pdif-input symbol parameter pin name min. typ. max. unit test conditions v s signal amplitude spdi, spdi2, 200 500 1000 mv pp f s1 biphase frequency spdi, spdi2 3.072 mhz 1000 ppm, f s = 48 khz f s2 biphase frequency spdi, spdi2 2.822 mhz 1000 ppm, f s = 44.1 khz f s3 biphase frequency spdi, spdi2 2.048 mhz 1000 ppm, f s = 32 khz t p biphase period spdi, spdi2 326 ns at f s = 48 khz, (highest sampling rate) t r rise time spdi, spdi2 065nsat f s = 48 khz, (highest sampling rate) t f fall time spdi, spdi2 065nsat f s = 48 khz, (highest sampling rate) duty-cycle spdi, spdi2 40 50 60 % at ? 1 ? and f s =48 khz 90% 10% 90% 10% v s t p t r t f
advance information mas 3528e micronas 51 4.6.3.4. s/pdif-bus output characteristics fig. 4 ? 14: timing of the s/pdif-output symbol parameter pin name min. typ. max. unit test conditions f s1 biphase frequency spdifout 3.072 mhz f s = 48 khz f s2 biphase frequency spdifout 2.822 mhz f s = 44.1 khz f s3 biphase frequency spdifout 2.048 mhz f s = 32 khz t p biphase period spdifout 326 ns at f s = 48 khz, (highest sampling rate) t r rise time spdifout 0 2 ns c load =10pf t f fall time spdifout 0 2 ns c load =10pf duty-cycle spdifout 50 % at ? 1 ? and f s =48 khz 90% 10% 90% 10% v s t p t r t f
mas 3528e advance information 52 micronas 4.6.3.5. i 2 s bus characteristics ? input fig. 4 ? 15: serial input of continuous data stream (sii not used) fig. 4 ? 16: serial input of i 2 s-signal symbol parameter pin name min. typ. max. unit test conditions t siclk i 2 s clock input clock period sic 960 ns burst mode, mean data rate < 150 kbit/s t sidds i 2 s data setup time before falling edge of clock sic, sid 50 t siclk ? 100 ns t siddh i 2 s data hold time sic, sid 50 ns t siids i 2 s word strobe setup time before falling(/rising) edge of clock sic, sii 50 t siclk ? 100 ns t siidh i 2 s word strobe hold time sic, sii 50 ns t bw burst wait time sic, sid 480 ns h l h l h l sic (sii) sid t siclk t siddh t sidds h l h l h l sic (sii) sid t siclk t siddh t sidds
advance information mas 3528e micronas 53 fig. 4 ? 17: schematic timing of the serial audio input (i 2 s). for the continuous data input mode, sii must be held low and data values are latched at falling clock edges. 302928272625...76543210 31302928272625 76543210 left 32-bit audio sample right 32-bit audio sample sic sid sii i2s v h v l v h v l v h v l ... ... 31 ... data valid at falling edge of clock
mas 3528e advance information 54 micronas 4.6.3.6. i 2 s characteristics ? output fig. 4 ? 18: i 2 s-output fig. 4 ? 19: schematic timing of the sdo interface in 32 bit/sample mode symbol parameter pin name min. typ. max. unit test conditions t sclko i 2 s clock output frequency soc 325 ns 48 khz sample rate 2 32 bits/sample t soiss i 2 s word strobe hold time after falling edge of clock soc, soi 10 t sclko /2 ns t soodc i 2 s data hold time after falling edge of clock soc, sod 10 t sclko /2 ns h l h l h l soc soi sod t sclko t soiss t soiss t soodc 302928272625...76543210 31302928272625 76543210 left 32-bit audio sample right 32-bit audio sample soc sod soi v h v l v h v l v h v l ... ... 31 ...
advance information mas 3528e micronas 55 4.6.4. firmware characteristics symbol parameter pin name min. typ. max. unit test conditions synchronization times for dolby digital mode t ddsync synchronization on dolby digital bit streams 140 ms f s = 48 khz, ac-3 synchronization times for mpeg-mode t mpgsync synchronization on mpeg bit streams 120 48 ms f s = 48 khz, mpeg ranges pllrange tracking range of sampling clock recovery pll ? 200 200 ppm
mas 3528e advance information 56 micronas fig. 4 ? 20: part 1 of the application circuit diagram. for details, please refer to the mas 3528e application kit. sync
advance information mas 3528e micronas 57 fig. 4 ? 21: part 2 of the application circuit diagram. for details, please refer to the mas 3528e application kit.
mas 3528e advance information 58 micronas
advance information mas 3528e micronas 59
all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas gmbh does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. mas 3528e advance information 60 micronas micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-509-1ai 5. data sheet history 1. advance information: ? mas 3528e dolby digital and mpeg-1 layer-2 audio decoder ? , june 28, 2000, 6251-509-1ai. first release of the advance informa- tion.
micronas page 1 of 8 subject: data sheet concerned: supplement: edition: advance information supplement data sheet errata mas 3528e (for advance information: edition june 28, 2000; 6251-509-1ai) the definition of the following sections and registers is missing or incorrect; section, table and figure numbers corre- spond to the data sheet. 2.7.5. frame synchronization for microprocessor interrupts, a frame synchronization output pin (sync) is provided. after decoding a valid header, the sync pin level changes to high. most of the status information (uis cells in table 3?6 on page 24) is updated now. to generate an edge for the controller, the level changes to low during pro- cessing the next header. after having completed this, the sync pin level changes to high again. if the level is low for more than 1 ms, no decoding is performed. memory cell uih_last_message (d0:13ff) provides background information thereof. 2.9.6. pcm audio data pcm-data are received via s/pdif or i 2 s. sampling frequency will be detected automatically and mirrored in d0:13a0 (uis_fs_code). if the pcm-data are received via i 2 s-bus the mas 3528e expects a valid wordstrobe, and i/o-control (d0:13d0) has to be set as described in table 3-7. in this case the deemphase must be activated by controller if necessary. 2.9.10.1. extra stereo output for headphone and vcr-recordings, an extra stereo output is provided that may be switched from lt/rt (surround encoded, default) to lo/ro (headphone encoded) . both, the 6-channel output and the stereo signal are routed to the serial data output interface . note : the stereo output is a downmix of the 6-channel output. so the stereo downmix will work properly only, if out- put mode (d0:13d6) (which effects the dolby downmix of the 6 channels) is in its default state (3/2-no downmix). data sheet errata for mas 3528e mas 3528e 6251-509-1ai, edition june 28, 2000 no. 1/ 6251-509-1ais dec. 20, 2000 mas 3528e
mas 3528e advance information supplement page 2 of 8 micronas table 3 ? 6: status memory cells memory address (hex) function mode name d0:13a0 sample rate of input bitstream dolby digital mpeg pcm (table 5.1 of atsc spec. a/52) bit[1:0] 00 48 khz 01 44.1 khz 10 32 khz 11 not detected (default) uis_fscod table 3 ? 7: configuration memory cells memory address (hex) functionmode reset value (hex) name d0:13d0 input and mode selection all bit[9] s/pdif or i 2 s input select 0 s/pdif input 1i 2 s input bit[8] i 2 s input select 0i 2 s input at sid (word mode) 1 continuos data stream at sid (sii connected to ground) bit[7:6] input data type 00 auto-detection 01 ac-3 (dolby digital) 10 mpeg layer-2 11 pcm 00000 uic_io_control output interface mode all bit[5] 0 default 1i 2 s output mode: invert wordstrobe bit[1] i 2 s output channels 08 1 channels 14 2 channels the clock and word strobe outputs soc and soi apply to all 4 data outputs sod...sod3 bit[0] i 2 s output mode 0 no delay (as used in sony mode) 1 delay of data related to wordstrobe slope (as used in philips mode)
micronas page 3 of 8 advance information supplement mas 3528e d0:13d6 output mode control (dolby downmix) dolby digital (section7.8 of atsc spec. a/52) bit[4:3] dual mono setting of dolby c decoder, applicable only if audio coding mode is dual mono (acmod = 0). the actual mixing depends on the number of available output channels (speakers). 00 stereo (straight output of both channels) 01 left mono (channel 1) 10 right mono (channel 2) 11 mixed mono (sum of both channels) bit[2:0] listening mode selector defines the number of available (desired) output channels (loudspeakers). 000 2/0 l, r dolby surround compatible 001 1/0 c 010 2/0 l, r 011 3/0 l, c, r 100 2/1 l, r, s 101 3/1 l, c, r, s 110 2/2 l, r, sl, sr 111 3/2 l, c, r, sl, sr these downmixing options are independent of the setting of the stereo output (d0:13de). but only in default setting (mode 2/3) the two stereo output (can be seen as an extra downmix) is done properly. undesired channels can be muted by setting the volume to zero or by muting the outputs in the dpl 4519g or msp 4450g, respec- tively. only listening modes 1/0, 2/0, and 3/0 should be used if dual mono is selected. 00007 uic_out_mode_ control d0:13db not longer required: do not write on this memory address d0:13e1 d0:13e2 d0:13e3 d0:13e4 d0:13e5 d0:13e6 d0:13e7 d0:13e8 volume control all volume left channel volume center channel volume right channel volume surround left channel volume surround right channel volume subwoofer channel volume stereo left channel volume stereo right channel bit[15:8] 7f hex +12 db ... 73 hex 0db ... 01 hex ? 114 db 00 hex mute the resolution is 1 db/step. 07300 (all) uic_l_volume uic_r_volume uic_sl_volume uic_sr_volume uic_c_volume uic_lfe_volume uic_l_st_volume uic_r_st_volume table 3 ? 7: configuration memory cells memory address (hex) functionmode reset value (hex) name
mas 3528e advance information supplement page 4 of 8 micronas table 3 ? 8: hybrid user interface cells memory address (hex) function reset value (hex) name d0:13ff message constants all messages bit[19:0] 0 no error 8 all errors with an error number higher or equal to this error number cause a restart 9 s/pdif: sync lost during look for pa, pb, pc, pd 10 s/pdif: sync lost during operation 11 data stream error (pa not correct) 12 data stream error (pb not correct) 13 data stream error (pc not correct) 14 data stream error (pd to big) 15 i2s timeout error 16 no input data type selected in i2s input mode (i.e. auto-detection is on) 17 input type over spdif changed from pcm to data 18 ac-3: initial waiting time out 19 ac-3: sync waiting time out 20 ac-3: sync lost 21 ac-3: header corrupted 22 ac-3: crc1 wait timeout 23 ac-3: crc1 fail 24 ac-3: crc2 wait timeout 25 ac-3: crc2 fail 26 selected bit-stream-number not available 27 pcm recognition inconsistent, restart 28 data type in burstinfo not ac-3, pcm, mpeg, or dts. 29 ac-3 - sampling frequency changed 30 invalid exponents detected 31 s/pdif: input type chosen manually (not autodetected) 32 ac3: input buffer overrun - the input pointer overwrites the actual frame 40 mpeg: sampling frequency changed 41 mpeg: no header found 42 mpeg: no layer 2 header found 43 mpeg: restart forced 44 mpeg: not enough data to decode 45 mpeg: s/pdif error 46 mpeg: decoding error 47 mpeg: input timeout 48 mpeg: sync error ... 00000 uih_last_ message
micronas page 5 of 8 advance information supplement mas 3528e d0:13ff (continued) [50:66] user interface messages 50 lm_user_change 51 lm_io_control 52 lm_noise 53 lm_c_delay 54 lm_sl_delay 55 lm_rl_delay 56 lm_out_lfe 57 lm_out_mode_control 58 lm_compression_control 59 lm_cut_x 60 lm_boost_y 61 lm_post_processing 62 lm_samp_freq 63 lm_outn_channels 64 lm_karaoke_mode 65 lm_downmix_mode 66 lm_out_clk_scale 70 pcm: sampling frequency changed in pcm mode the latest message that occurred is displayed in this cell. the con- troller should frequently (e.g. once per frame) check this memory location. after reading the message it is recommended to clear this cell (by writing a ? 0 ? ) to see whether this message occures again. 00000 uih_last_ message table 3 ? 8: hybrid user interface cells memory address (hex) function reset value (hex) name
mas 3528e advance information supplement page 6 of 8 micronas fig. 4 ? 20: part 1 of the application circuit diagram. for details, please refer to the multichannel audio application kit.
micronas page 7 of 8 advance information supplement mas 3528e fig. 4 ? 21: part 2 of the application circuit diagram. for details, please refer to the multichannel audio application kit.
mas 3528e advance information supplement page 8 of 8 micronas

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